The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for monitoring and managing the aging of silicon in an integrated circuit device.
Integrated circuit designers plan for the aging or power-on hours (POH) of silicon in integrated circuit devices based on modeling various degradations to the silicon with degradation dependent on, for example, unique characteristics that arise from manufacturing, such as effective gate conductor length (Lpoly) of critical circuits for a given chip or wafer (L) and a magnitude coefficient that varies by wafer or lot (A), and run-time operational characteristics experienced by the silicon, such as junction temperature (T), frequency of operation (F), which is often augmented by a generic switching factor assumption (FR), and voltage of operation (Vds).
An estimated lifetime of the silicon assumes a static ‘worst case’ combination of design characteristics and conditions of operation. However, most shipped integrated circuit devices will never hit this POH limit. Therefore, operating integrated circuit devices under ‘worst case’ scenarios may result in very conservative (high energy inefficient) voltages, operating frequencies, required cooling, or the like, in the design for most components within such integrated circuit devices. Further, other integrated circuit devices may be erroneously discarded when their determined effective gate conductor length (Lpoly) of critical circuits for a given chip or wafer (L) and/or a magnitude coefficient that varies by wafer or lot (A) lead to unacceptable POH based on the ‘worst case’ scenarios of static assumptions on operational characteristics.